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High-Performance
Routers
Existing or
earlier proposed routers often lacks scalability because they utilize a
shared backplane bus or crossbar to interconnect line cards (LC's) and
forwarding engines (FE's). Their packet classification mechanisms could
easily become performance bottlenecks, as the router's speed increases
or the routing/filter table sizes grow. This project investigates router
architecture with good scalability and capable of forwarding hundreds of
millions of packets per second, in order to keep up with future
transmission technologies. It aims to help advance the state-of-the-art
of router design and to enable large networking configurations.
Current
routers rely on enhanced software search algorithms or specific hardware
support to meet the IP address lookup rate (of up to 5 million lookups
per second per lookup unit), but a future high-speed network calls for
routers with aggregate lookup rates of some two orders of magnitude
higher than a lookup unit presently can offer. Hardware-assisted
mechanisms for fast packet forwarding appear promising. In particular,
the use of caches to hold lookup results can fulfill subsequent lookup
requests for identical destinations immediately without resorting to
FE's for lookups, reducing the mean lookup latency tremendously. Unlike
other software- or hardware-based forwarding improvement approaches, our
hardware-assisted mechanisms can be effectively applicable to both IPv6
and IPv4, ideally suitable for scalable high-performance routers.
Publications:
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N.-F. Tzeng, Routing Table Partitioning for Speedy Packet Lookups in Scalable Routers,
IEEE Transactions on Parallel and Distributed Systems, vol. 17, May 2006, pp. 481-494.
Abstract,
PDF (1740K).
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G. Wang and N.-F. Tzeng, TCAM-Based Forwarding Engine with Minimum Independent Prefix Set (MIPS) for Fast Updating,
2006 IEEE Int'l Conf. on Communications (ICC '06), June 2006.
PDF (255KB).
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M. Mandviwalla and N.-F. Tzeng, Energy-Efficient Scheme for Multiprocessor-Based Router Linecards,
Proc. 2006 Symposium on Applications and the Internet (SAINT 2006), Jan. 2006, pp. 156-163.
Abstract,
PDF (384KB).
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N.-F. Tzeng, SPAL: A Speedy Packet Lookup Technique for High-Performance Routers,
Proc. 33rd International Conference on Parallel Processing, Aug. 2004, pp. 284-291.
Abstract,
PDF (990KB).
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M. Mandviwalla and N.-F. Tzeng, DRA: A Dependable Architecture for High-Performance Routers,
Proc. International Workshop on Network Design and Architecture (IWNDA 2004, held in conjunction with 33rd
International Conference on Parallel Processing), Aug. 2004, pp. 265-272.
Abstract,
PDF (350KB).
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N.-F. Tzeng, Multistage-Based Switching Fabrics for Scalable Routers,
IEEE Transactions on Parallel and Distributed Systems, vol. 15, April 2004, pp. 304-318.
Abstract,
PDF (1250K).
N.-F. Tzeng, Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers,
Proc. 2003 International Conference on Parallel Processing, Oct. 2003, pp. 11-18.
Abstract,
PDF (387K). N.-F. Tzeng and M. Mandviwalla, Performance Evaluation of Router Switching Fabrics,
Proc. 9th IEEE International Conference on Parallel and Distributed Systems, December 2002, pp. 542-547.
Abstract,
PDF (282K).
N.-F. Tzeng and R. Batchu, Design and Evaluation of Scalable Switching Fabrics for High-Performance Routers,
Proc. 31st International Conference on Parallel Processing, August 2002, pp. 167-174.
Abstract,
PDF (521K).
N.-F. Tzeng and M. Mandviwalla, Cost-Effective Switching Fabrics with Distributed Control for Scalable Routers,
Proc. 22nd IEEE International Conference on Distributed Computing Systems, July 2002, pp. 65-73.
Abstract,
PDF (513K).
K. Vibhatavanij, N.-F. Tzeng, and A. Kongmunvattana, Simultaneous Multithreading-Based Routers,
Proc. 29th International Conference on Parallel Processing (ICPP '00), Aug. 2000, pp. 362-369.
Abstract,
PDF (738K).
N.-F. Tzeng, K. Ponnuru, and K. Vibhatavanij, A Cost-Effective Design for ATM Switching Fabrics,
Proc. 1999 IEEE International Conference on Communications (ICC '99), June 1999, pp. S37.4.1-5.
Abstract,
PDF (81K).
Patents:
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