Colloquium, "Exploring Scalable Wireless NoC Microarchitecture for Chip Multiprocessors", Dr. Danella Zhao

Abstract

Chip Multiprocessor (CMP) designs are rapidly emerging, where dozens or hundreds of processors are integrated on a single die. Such CMP devices allow superior performance gains while side-stepping the power and heat dissipation limitations of clock frequency scaling. The main advantage lies in the exploitation of parallelism, distributively and massively. Consequently, the on-chip communication fabric becomes the performance determinant. To bridge the widening gap between computation requirements and communication efficiency faced by gigascale CMPs in the upcoming billion-transistor era, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed by using the recently developed RF interconnect technology. With the high data-rate, low power and ultra-short range interconnection provided by UWB technology, the WNoC design paradigm calls for effective solutions to overhaul the on-chip communication infrastructure of nanoscale CMPs. In this talk, I will present the feasibility study of WNoC from various aspects, physical layer exploration, system architecture design, RF microarchitecture development and hardware implementation.

DATE: FRIDAY, OCTOBER 16, 2009
TIME: 11:00 A.M. - 12:00 NOON
LOCATION: ACTR AUDITORIUM, ROOM 112